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HSP45314
TM
Data Sheet
May 2000
File Number
4820.2
CommLinkTM Direct Digital Synthesizer
The 14-bit HSP45314 provides a complete Direct Digital Synthesizer (DDS) system in a single 48-pin LQFP package. A 48-bit Programmable Carrier NCO (numerically controlled oscillator) and a high speed 14-bit DAC (digital to analog converter) are integrated into a stand alone DDS. The DDS accepts 48-bit center and offset frequency control information via a parallel processor interface. Modulation control is provided by 3 external pins. The PH0 and PH1 pins select phase offsets of 0, 90, 180 and 270 degrees, while the ENOFR pin enables or zeros the offset frequency word to the phase accumulator. The parallel processor interface has an 8-bit write-only data input C(7:0), a 4-bit address A(3:0) bus, a Write Strobe (WR), and a Write Enable (WE). The processor can update all registers simultaneously by loading a set of master registers, then transfer all master registers to the slave registers by asserting the UPDATE pin.
Features
* 125MSPS Output Sample Rate with 5V Digital Supply * 100MSPS Output Sample Rate with 3.3V Digital Supply * 14-bit DAC with Internal Reference * Parallel Control Interface for Fast Tuning (50MSPS Control Register Write Rate) * 48-bit Programmable Frequency Control * Small 48-pin LQFP package
Applications
* Programmable Local Oscillator * FSK Modulation * Direct Digital Synthesis * Clock Generation
Ordering Information
PART NUMBER HSP45314VI TEMP. RANGE (oC) -40 to 85 PACKAGE 48 LQFP PKG. NO. Q48.7X7A
Block Diagram
COMPOUT
C(7:0) A(3:0) WR WE UPDATE
Pinout
C3 C4 C5 C6 C7 DVDD WR DGND WE NC A0 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 2 34 3 33 4 32 5 31 6 HSP45314 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 1 + ININ+ COMP1 COMP2
MASTER MODULATION CONTROL
SLAVE
PHASE ACCUM.
48-PIN LQFP (Q48.7X7A TOP VIEW
SINE WAVE ROM
ENOFR PH(1:0)
14 BIT DAC INT REF
IOUTA IOUTB REFIO REFLO
RESET CLK
C2 C1 C0 ENOFR DGND CLK DVDD RESET UPDATE COMPOUT REFLO REFIO
A2 A3 PH0 PH1 DGND DVDD DGND DGND DGND DGND DVDD DGND
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 CommLinkTM is a trademark of Intersil Corporation.
FSADJ COMP1 AGND AGND IOUTB IOUTA COMP2 AVDD AGND IN+ INAGND
HSP45314 Typical Application Circuit (Sinewave Generation)
WRITE CLOCK WRITE ENABLE PH1:PH0 BUS A3:A0 BUS C7:C0 BUS
PROCESSOR/
FPGA/CPLD
CLOCK SOURCE DVPP
0.1F
C2 C1 C0 ENOFR DGND CLK DVDD RESET UPDATE COMPOUT REFLO REFIO 0.1F
48 47 46 45 44 43 42 41 40 39 38 37 36 35 2 34 3 33 4 32 5 31 6 HSP45314 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 1
C3 C4 C5 C6 C7 DVDD WR DGND WE NC A0 A1
A2 A3 PH0 PH1 DGND DVDD DGND DGND DGND DGND DVDD DGND
DVPP
0.1F DVPP
0.1F
FSADJ COMP1 AGND AGND IOUTB IOUTA COMP2 AVDD AGND IN+ INAGND
0.1F RSET 2k 0.1F AVPP 0.1F
AVPP
50 50
(IOUTA) ANALOG OUTPUT
FERRITE BEAD DVPP (DIGITAL POWER PLANE) + 10F +5V POWER SOURCE FERRITE BEAD + 10F AVPP (ANALOG POWER PLANE) 10H 0.1F 1F 10H 0.1F 1F
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HSP45314 Functional Description
The HSP45314 is an NCO with an integrated 14-bit DAC designed to run in excess of 125MSPS. The NCO is a 16-bit output design, which is rounded to 14 bits for input to the DAC. The frequency control is the sum of a 48-bit center frequency word and a 48-bit offset frequency word. The two components are added modulo 48 bits with the alignment shown in Table 1. Each of the two terms can be zeroed independently (via the microprocessor interface for the center frequency and via the ENOFR pin for the offset frequency term).
Parallel Interface
The processor interface is an 8-bit parallel write only interface. The interface consists of 8 data bits (C7:C0), four address pins (A3:A0), a Write Strobe (WR), and a Write Enable (WE). The interface is a master/slave type. The processor interface loads a set of master registers. The contents of the master set of registers is then transferred to a slave set of registers by asserting a pin (UPDATE). This allows all of the bits of the frequency control to be updated simultaneously. The rate which the user writes (WR) to these registers does not have to be the same rate as the DDS clock rate (the rate of the NCO and DAC; pin CLK). It is expected that most applications will have a slower register write rate than the DDS clock rate. It takes 6 WR cycles at the write rate plus another 11 CLK cycles at the DDS rate to write and obtain a new frequency, assuming that all registers are rewritten and the UPDATE pin is always active. If the UPDATE pin is not active until after the new word has been written, it takes 14 CLK cycles, rather than 11. For cases which require the output to be updated with all of the new frequency information present, it is necessary that the UPDATE be inactive until after all of the new frequency word has been written to the device. See the Timing Diagrams for more information. The parallel registers can be written to again immediately after the 11th or 14th CLK cycle, again depending the state of UPDATE. If the application does not need 48 bits (all 6 registers) of frequency information, then the output frequency can be changed more quickly. For example, if only 32 bits of frequency information are needed and it is desired that the output be updated all at once, then it takes 4 WR cycles, then the assertion low of the UPDATE pin, plus another 14 CLK cycles at the DDS rate to write and update a new frequency. The timing is the same whether writing to the center or offset frequency registers. For faster frequency update, consider the ENOFR (Enable Offset Frequency Register) option. Once the values have been written to the center and offset frequency registers, the user can enable and disable the offset frequency register, which is added to the center frequency value when enabled. The ENOFR pin has a latency of 14 CLK cycles, but simplifies the interface because the only pin that has to be toggled is the ENOFR pin.
Frequency Generation
The output frequency of the part is determined by the summation of two registers: fOUT = fCLK x ( (CF + OF) mod (248))/ (248), where CF is the Center Frequency register and OF is the Offset Frequency register. With a 125MSPS clock rate, the center frequency can be programmed to (125 x 106)/(248) = 0.4 Hz resolution. The addition of the frequency control words can be interpreted as two's complement if convenient. For example, if the center frequency is set to 4000...00h and the offset frequency set to C000..00h, the programmed center frequency would be fCLK/4 and the programmed offset frequency -fCLK/4. The sum would be 10000..00h, but because only the lower 48 bits are retained, the effective frequency would be 0. In reality, frequencies above 8000...00h alias below fCLK/2 (the output of the part is real), so the MSB is only provided as a convenience for two's complement calculations. The frequency control of the NCO is the change in phase per clock period or d/dt. This is integrated by the phase accumulator to obtain frequency. The most significant 24 bits of phase are then mapped to 16 bits of amplitude in a sine look-up table function. The range of d/dt is 0 to 1 with 1 equaling 360 degrees or (2 x pi) per clock period. The phase accumulator output is also 0 to 1 with 1 equaling 360 degrees. The operations are modulo 48 bits because the MSB (bit 47) aligns with the most significant address bit of the sine ROM and the ROM contains one cycle of a sinusoid. The MSB is weighted at 180 degrees. Full scale is 360 degrees minus 1 LSB and the phase then rolls over to 0 degrees for the next cycle of the sinusoid.
TABLE 1. FREQUENCY CONTROL BIT ALIGNMENTS Bits Individual Bit Alignment Phase Accumulator Center Frequency Offset Frequency 4444 4444 7654 3210 xxxx xxxx xxxx xxxx xxxx xxxx 3333 3333 9876 5432 xxxx xxxx xxxx xxxx xxxx xxxx 3322 2222 1098 7654 xxxx xxxx xxxx xxxx xxxx xxxx 2222 1111 3210 9876 xxxx xxxx xxxx xxxx xxxx xxxx 1111 1100 5432 1098 xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 7654 3210 xxxx xxxx xxxx xxxx xxxx xxxx
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HSP45314
Control Pins
There are three control pins provided for phase and frequency control. The PH0 and PH1 pins select phase offsets of 0, 90, 180, and 270 degrees and can be used for low speed, unfiltered BPSK or QPSK modulation. These pins can also be used for providing sine/cosine when using two HSP45314s together as quadrature local oscillators. The ENOFR pin enables or zeros the offset frequency word to the phase accumulator and can be used for FSK or MSK modulation. These control pins and the UPDATE pin are passed through special cells to minimize the probability of meta-stability. If the internal reference is used, VFSADJ will equal approximately 1.2V (pin 13). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32.
Analog Output
IOUTA and IOUTB are complementary current outputs. They are generated by a 14-bit digital-to-analog converter (DAC) that is capable of running at the full 125MSPS rate. The DDS clock also clocks the DAC. The sum of the two output currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -1.0V to 1.25V. RLOAD (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD. These outputs can be used in a differential-to-single-ended arrangement. This is typically done to achieve better harmonic rejection. Because of a mismatch in IOUTA and IOUTB, the transformer does not improve the harmonic rejection. However, it can provide voltage gain without adding distortion. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DDS (see Figure 1). With the center tap grounded, the output swing of pins 17 and 18 will be biased at zero volts. The loading as shown in Figure 1 will result in a 500mVPP signal at the output of the transformer if the full scale output current of the DAC is set to 20mA.
R EQ IS THE IMPEDANCE LOADING EACH OUTPUT 50 PIN 17 IOUTB 100 PIN 18 HSP45314 IOUTA 50 50 REPRESENTS THE SPECTRUM ANALYZER VOUT = (2 x IOUT x REQ)VPP 50
Reset
A RESET pin is available which resets all registers to their defaults. In order to reset the part, the user must take the RESET pin low, allow at least one CLK rising edge, and then take the RESET pin high again. The latency from the RESET pin going high until the output reflects the reset is 11 CLK cycles. See the register description table in the back of the datasheet for the default states of all bits in all addresses. After RESET goes high, one rising edge of CLK is required before the control registers can be written to again.
Comparator
A comparator is provided for square wave output generation. The user can take the DDS analog output, filter it, and then send it back into the comparator. A square wave will be generated at the comparator output (COMPOUT pin) at an amplitude level that is dependent on the digital power supply used (DVDD). The comparator was designed to operate at speeds comparable to the DDS output frequency range (approximately 0-50MHz). It is not intended for low jitter applications. The comparator has a sleep mode that is activated by connecting both inputs (IN- and IN+) to the analog power supply plane. This will save approximately 4mA of current (as shown in the Typical Application Circuit). If the comparator is not used, leave the COMPOUT pin floating.
DAC Voltage Reference
The internal voltage reference for the DAC has a nominal value of +1.2V with a 60ppm/ oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1F capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (11) selects the reference. The internal reference can be selected if pin 11 is tied low (ground). If an external reference is desired, then pin 11 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 12. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation.
FIGURE 1.
VOUT = 2 x IOUT x REQ, where REQ is ~12.5. Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset, which could limit the voltage swing available due to the output voltage compliance range. The 50 load on the output of the transformer represents the load at the end of a
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HSP45314
`transmission line', typically a spectrum analyzer, oscilloscope, or the next function in the signal chain. The necessity to have a 50 impedance looking back into the transformer is negated if the DDS is only driving a short trace. The output voltage compliance range does limit the impedance that is loading the DDS output.
Improving SFDR
As was previously noted, using +5V power supplies provides the best SFDR. Under some clock and output frequency combinations, particularly when the fCLK/fOUT ratio is less than 4, the user can improve SFDR even further by connecting the COMP2 pin (19) of the DDS to the analog power supply. The digital supply must be +5V if this option is explored. Improvements as much as 6dBc in the SFDR-toNyquist measurement were seen in the lab.
Ground Plane Considerations
Separate digital and analog ground planes should be used. All of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Pins 11 through 24 are analog pins, while all of the others are digital.
FSK Modulation
BFSK (Binary Frequency Shift Keying) can be done by enabling and disabling the offset frequency (ENOFR pin). Once the offset frequency has been written once, it can be toggled with a latency of 14 CLK cycles. M-ary FSK or GFSK can be done by continuously loading in new frequency words.
Noise Reduction Considerations
To minimize power supply noise, 0.1F capacitors should be placed as close as possible to the power supply pins, AVDD and DVDD. Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended.
Quadrature Local Oscillators
Two HSP45314s can be used as sine/cosine generators for quadrature local oscillator applications. It is important to note that the Phase Accumulator feedback needs to be zeroed in both devices if it is desired that both DDSs restart with a known phase, which is determined by the use of the phase control pins, PH1 and PH0. To zero the phase accumulator, pull bit 5 of address 13 low and then high again at the same time in both devices.
Power Supplies
The DDS will provide the best SFDR (Spurious Free Dynamic Range) when using +5V analog and +5V digital power supply. The analog supply must be +5V (10%). The digital supply can be either a +3.3V (10%) or a +5V (10%) supply, or anything in between. The DDS is rated to 125MSPS when using a +5V digital supply. The maximum clock is 100MSPS when using a +3.3V digital supply.
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HSP45314
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DGND . . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to AGND . . . . . . . . . . . . . . . . . . +5.5V Grounds, AGND To DGND. . . . . . . . . . . . . . . . . . . . . -0.3V To +0.3V Digital Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . DVDD + 0.3V Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA(oC/W) LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values HSP45314 TA = -40oC TO 85oC
PARAMETER DAC CHARACTERISTICS DAC Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error Full Scale Gain Drift Full Scale Output Current Output Voltage Compliance Range DAC DYNAMIC CHARACTERISTICS Maximum Clock Rate, fCLK Maximum Clock Rate, fCLK Output Settling Time, (tSETT) Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA
TEST CONDITIONS
MIN
TYP
MAX
UNITS
14 "Best Fit" Straight Line (Note 7) (Note 7) (Note 7) (Note 7) With Internal Reference (Notes 2, 7) With Internal Reference (Note 7) (Note 3) (Note 3, 7) -5 -2 -0.025 -10 2 -1.0
+2.5 +1.5
+6 +4 +0.025
Bits LSB LSB % FSR ppm FSR/oC % FSR ppm FSR/oC mA V
0.1 1 50 -
+10 20 1.25
+5V DVDD , +5V AVDD (Note 3) +3.3V DVDD , +5V AVDD (Note 3) 0.05% (8 LSB) (Note 7) Full Scale Step Full Scale Step
125 100 -
35 2.5 2.5 25 50 30
-
MSPS MSPS ns ns ns pF pA/Hz pA/Hz
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HSP45314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HSP45314 TA = -40oC TO 85oC PARAMETER AC CHARACTERISTICS Spurious Free Dynamic Range, SFDR Within a Window (Notes 4, 7) fCLK = 100MSPS, fOUT = 20MHz, 5MHz Span fCLK = 100MSPS, fOUT = 5MHz, 8MHz Span fCLK = 50MSPS, fOUT = 5MHz, 8MHz Span Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) (Notes 4, 7) fCLK = 125MSPS, fOUT = 40.4MHz fCLK = 125MSPS, fOUT = 10.1MHz fCLK = 125MSPS, fOUT = 5.02MHz fCLK = 100MSPS, fOUT = 40.4MHz fCLK = 100MSPS, fOUT = 20.2MHz fCLK = 100MSPS, fOUT = 5.04MHz fCLK = 100MSPS, fOUT = 2.51MHz fCLK = 50MSPS, fOUT = 20.2MHz fCLK = 50MSPS, fOUT = 5.02MHz fCLK = 50MSPS, fOUT = 2.51MHz fCLK = 50MSPS, fOUT = 1.00MHz fCLK = 25MSPS, fOUT = 1.0MHz DAC REFERENCE VOLTAGE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 7) DIGITAL INPUTS Input Logic High Voltage with 5V Digital Supply, VIH Input Logic High Voltage with 3V Digital Supply, VIH Input Logic Low Voltage with 5V Digital Supply, VIL Input Logic Low Voltage with 3V Digital Supply, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN (Note 3) (Note 3) (Note 3) (Note 3) 3.5 2.0 -10 -10 5 3 0 0 4 1.3 0.8 +10 +10 V V V V A A pF Pin 13 Voltage with Internal Reference 1.13 1.2 60 0.1 1 1.4 1.28 V
ppm/oC
TEST CONDITIONS
MIN
TYP
MAX
UNITS
57 -
93 93 93 40 63 72 40 49 72 73 45 68 72 71 72
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
A M MHz
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HSP45314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HSP45314 TA = -40oC TO 85oC PARAMETER TIMING CHARACTERISTICS Maximum Clock Rate, fCLK Maximum Clock Rate, fCLK CLK Pulse Width, tCW Maximum Parallel Write Rate WR Pulse Width, tWW Data Setup Time, tDS Data Hold Time, tDH Address Setup Time, tAS Address Hold Time, tAH UPDATE Pulse Width, tUW UPDATE Setup Time, tUS UPDATE Hold Time, tUH UPDATE Latency, tUL UPDATE Latency, tUL Phase Pulse Width, tPW Phase Setup Time, tPS Phase Hold Time, tPH Phase Latency, tPL ENOFR Pulse Width, tEW ENOFR Setup Time, tES ENOFR Hold Time, tEH ENOFR Latency, tEL Write Enable Pulse Width, tWR Write Enable Setup Time, tWS Write Enable Hold Time, tWH RESET Pulse Width, tRW RESET Setup Time, tRS RESET Latency to Output, tRL RESET Latency to Write, tRE +5V DVDD , +5V AVDD (Note 3) +3.3V DVDD , +5V AVDD (Note 3) CLK (Note 3) Rate of WR (Note 3) Between DATA and WR (Note 3) Between DATA and WR (Note 3) Between ADDR and WR (Note 3) Between ADDR and WR (Note 3) (Note 3) Between UPDATE and CLK (Note 3) Between UPDATE and CLK (Note 3) After UPDATE, before analog output change, if asserted after writing to the control registers After UPDATE, before analog output change, if asserted before writing to the control registers PH(1:0) (Note 3) Between PH(1:0) change and CLK (Note 3) Between PH(1:0) change and CLK (Note 3) Between PH(1:0) change and analog output change ENOFR (Note 3) Between ENOFR and CLK (Note 3) Between ENOFR and CLK (Note 3) After ENOFR, before analog output change WE (Note 3) Between WE and WR (Note 3) Between WE and WR (Note 3) RESET (Note 3) Between RESET and CLK After RESET, before analog output reflects reset values After RESET, before the control registers can be written to 125 100 5 50 5 10 0 12 0 5 2 4 5 2 4 5 2 4 5 2 4 5 14 11 12 14 2 11 1 MSPS MSPS ns MSPS ns ns ns ns ns ns ns ns Clock Cycles Clock Cycles ns ns ns Clock Cycles ns ns ns Clock Cycles ns ns ns ns ns Clock Cycles Clock Cycles TEST CONDITIONS MIN TYP MAX UNITS
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HSP45314
Electrical Specifications
AVDD = DVDD = +5V (unless otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) HSP45314 TA = -40oC TO 85oC PARAMETER COMPARATOR CHARACTERISTICS Input Capacitance Input Resistance Input Current Maximum Input Voltage Allowed (Excluding comparator sleep mode) 2.6 4 >1 1 4.0 0.1 6 5 1.5 1.3 100 3.75 0.4 pF M A V Vpp ns ns ns ns V V MHz TEST CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage, Peak-to-Peak (Dependent on noise) Propagation Delay, High to Low Propagation Delay, Low to High Output Rise Time Output Fall Time Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Toggle Rate (Note 8) (Note 8) (Note 8) (Note 8) IOH = -4mA IOL = +4mA High Z Load (~1M)
POWER SUPPLY CHARACTERISTICS AVDD (Analog) Power Supply DVDD (Digital) Power Supply Analog Supply Current (IAVDD) 5V, IOUTFS = 20mA (Note 10) 5V, IOUTFS = 2mA Digital Supply Current (IDVDD) 5V (Notes 5, 10) 3.3V (Notes 6, 9) Power Dissipation AVDD = 5V, DVDD = 3.3V, IOUTFS = 20mA (Notes 6, 9) AVDD = 5V, DVDD = 5V, IOUTFS = 20mA (Notes 5, 10) Power Supply Rejection NOTES: 2. Gain Error for the DAC is measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A); ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. 5. Measured with the clock at 125MSPS and the output frequency at 10MHz. 6. Measured with the clock at 100MSPS and the output frequency at 10MHz. 7. See "Definition of Specifications". 8. 50MHz, High Z Load (~1M), 15pF capacitance, (IN- = 0.5Vpp), (IN+ = 0.25VDC). 9. For maximum value, 5.5V AVDD and 3.6V DVDD are used. 10. For maximum value, 5.5V AVDD and 5.5V DVDD are used. Single 5V Supply (Note 7) 4.5 3.0 -0.2 5.0 3.3 25 7 90 50 290 625 5.5 5.5 30 100 55 363 715 +0.2 V V mA mA mA mA mW mW % FSR/V
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HSP45314 Definition of Specifications
Differential Non-Linearity, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1LSB. A DNL specification of 1LSB or less guarantees monotonicity. Integral Non-Linearity, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Full Scale Gain Drift, is measured by setting the DAC inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (Full Scale Range) per oC. Full Scale Gain Error, is the error from an ideal ratio of 32 between the DAC output current and the full scale adjust current (through RSET). Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. Offset Drift, is measured by setting the DAC inputs to all logic low (all 0s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (Full Scale Range) per degree oC. Offset Error, is measured by setting the DAC inputs to all logic low (all 0s) and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. The measurement is done by switching quarter scale. Termination impedance was 25 due to the parallel resistance of the 50 loading on the output and the oscilloscope's 50 input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed at either IOUTA or IOUTB does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The supply's nominal +5V is varied 10% and the change in the DAC full scale output current is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs to the DAC set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window.
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HSP45314 Timing Diagrams
WE tAS ADDR A0
tWS tAH A1 A2 A3 A4
tWH
A5
DON'T CARE
DATA
W0 tDS
W1 tDH
W2
W3
W4
W5
DON'T CARE
WRITE 6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD CLK
DON'T CARE
DON'T CARE tUS
UPDATE tUL = 14 CLK RISING EDGES tUD ANALOG OUT OLD FREQ NEW FREQ
FIGURE 2. PARALLEL-LOAD METHOD 1, UPDATE ACTIVE AFTER LOADING REGISTERS (RESET = HIGH)
WE tAS tAH
tWS
tWH
ADDR
A0
A1
A2
A3
A4
A5
DON'T CARE
DATA
W0 tDS
W1 tDH
W2
W3
W4
W5
DON'T CARE
WRITE t = 6 WRITE CYCLES MAX, 1 FOR EVERY 8 BIT WORD CLK
DON'T CARE
DON'T CARE
UPDATE
tUL= 11 CLK RISING EDGES
ANALOG OUT
PREVIOUS FREQ PARTIAL UPDATES
ENTIRE NEW FREQ
FIGURE 3. PARALLEL-LOAD METHOD 2, UPDATE ACTIVE WHILE LOADING REGISTERS (RESET = HIGH)
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HSP45314 Timing Diagrams
(Continued)
ONE CLK RISING EDGE REQUIRED WHILE RESET LOW
CLK
tRS RESET tRL = 11 CLK RISING EDGES
ANALOG OUT
PREVIOUS REGISTER VALUES
RESET REGISTER VALUES
FIGURE 4. RESET TIMING AND LATENCY
CLK
tEH ENOFR tES CENTER + OFFSET
ANALOG OUT
CENTER FREQUENCY ONLY
CENTER + OFFSET
CENTER ONLY
tEL = 14 CLK RISING EDGES
FIGURE 5. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH)
Pin Description
PIN NO. 44-48, 1-3 42 40 35-38 6 8 30 27 32 9 PIN NAME C(7:0) WR WE A(3:0) CLK RESET DGND DGND DGND UPDATE TYPE Input Input Input Input Clock Input (Input) (Input) (Input) Input PIN DESCRIPTION 8-bit Processor Input Data Bus. C7 is the MSB. Data is written to the control register selected on A(3:0) on the rising edge of WR when WE is active. Write Clock For The Processor Interface. Parallel data is clocked into the chip on the rising edge of WR. Write Enable. Active low. WE must be active when writing data to the chip. Processor Interface Address Bus. These pins select the destination register for data on the C(7:0) bus. A3 is the MSB. NCO and DAC Clock. The phase accumulator and DAC output update on the rising edge of this clock. CLK can be asynchronous to the WR clock. Reset. Active Low. Resets control registers to their default states (see register description table) and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur. Connect to DGND. Future serial clock input. Connect to DGND. Future serial data input. Connect to DGND. Future serial sync input. Active Low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0) pins. This pin is provided for updating an entire frequency word at once rather than byte by byte.
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HSP45314 Pin Description
PIN NO. 33, 34 (Continued) TYPE Input PIN DESCRIPTION Phase Offset Bits. The phase of the output is shifted. If not used, these pins should be grounded. 00 - 0 degrees reference 01 - 90 degrees shift 10 - 180 degrees shift 11 - 270 degrees shift Enable Offset Frequency. Active High. When high, the offset frequency bus is enabled to the phase accumulator. When low, the offset frequency bus is zeroed. This pin does not affect the contents of the offset frequency registers. If not used, the pin should be grounded. Comparator Output. Connect to analog ground to enable the DAC's internal 1.2V reference or connect to AVDD to disable the internal reference. Reference voltage input for the DAC if internal reference is disabled. Recommend the use of a 0.1F cap to ground from the REFIO pin when a DC reference voltage is used. Full Scale Current Adjust for the DAC. Use a resistor to ground (RSET) to adjust the full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET, where VFSADJ equals the reference voltage. Noise reduction for the DAC. Connect a 0.1F cap to AVDD plane. Noise reduction for the DAC. Connect a 0.1F cap to AGND plane. Output Output Power Gnd Power Gnd Input NC DAC Current Output. DAC Complementary Current Output. Analog Supply Voltage. Analog Ground. Digital Supply Voltage. Digital Ground. Comparator Inputs. To power down the comparator, connect both of these pins to the analog power supply. This will conserve ~4mA of current. No Connect.
PIN NAME PH(1:0)
4
ENOFR
Input
10 11 12 13
COMPOUT REFLO REFIO FSADJ
Output Input Input
14 19 18 17 20 15, 16, 21, 24 7, 26, 31, 43 5, 25, 28, 29, 41 22, 23 39
COMP1 COMP2 IOUTA IOUTB AVDD AGND DVDD DGND IN+, INNC
Control Register Description
ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 BITS 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 DESCRIPTION Center frequency bits CF(7:0) (Least Significant Byte). Center frequency bits CF(15:8). Center frequency bits CF(23:16). Center frequency bits CF(31:24). Center frequency bits CF(39:32). Center frequency bits CF(47:40) (MSByte). (Reset gives fCLK/4 output). Offset frequency bits OF(7:0) (LSByte). Offset frequency bits OF(15:8). Offset frequency bits OF(23:16). Offset frequency bits OF(31:24). Offset frequency bits OF(39:32). Offset frequency bits OF(47:40) (MSByte). RESET STATE 00 h 00 h 00 h 00 h 00 h 40 h 00 h 00 h 00 h 00 h 00 h 00 h
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HSP45314 Control Register Description
ADDRESS 12 BITS 7:1 0 (Continued) DESCRIPTION Bits 7 through 1 are Intersil reserved for future serial input control. Do Not Change. Center Frequency Enable. 1 = enable, 0 = center frequency disabled. This bit can be used to zero the center frequency (CF(47:0)) to the phase accumulator. This does not zero the processor interface registers - just the data path from the registers to the phase accumulator. NCO control word. Intersil reserved. Do Not Change. Intersil Reserved. Do Not Change. Future Serial output frequency register enable. Phase accumulator feedback. 0 = accumulator feedback disabled, 1 = accumulator enabled. Intersil reserved. Do Not Change. User should write 30 h to address 14 after RESET. NCO-to-DAC setup and hold time control. Set to 11b. RESET STATE 00 h 1b
13
7:0 7 6 5 4:0
F8 h 1b 1b 1b 11000 b 10 h 01 b
14
7:0 5:4
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